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| MCP3201 2.7V 12-Bit A/D Converter with SPITM Serial Interface Features * * * * * * * * * * * * * * 12-bit resolution 1 LSB max DNL 1 LSB max INL (MCP3201-B) 2 LSB max INL (MCP3201-C) On-chip sample and hold SPITM serial interface (modes 0,0 and 1,1) Single supply operation: 2.7V - 5.5V 100ksps max. sampling rate at VDD = 5V 50ksps max. sampling rate at VDD = 2.7V Low power CMOS technology 500 nA typical standby current, 2 A max. 400 A max. active current at 5V Industrial temp range: -40C to +85C 8-pin MSOP, PDIP, SOIC and TSSOP packages Package Types MSOP, PDIP, SOIC, TSSOP VREF IN+ IN- VSS 1 MCP3201 VREF 8 7 6 5 VDD CLK DOUT CS/SHDN 2 3 4 Functional Block Diagram VDD VSS Applications * * * * Sensor Interface Process Control Data Acquisition Battery Operated Systems DAC Comparator IN+ INSample and Hold Control Logic 12-Bit SAR Description The Microchip Technology Inc. MCP3201 is a successive approximation 12-bit Analog-to-Digital (A/D) Converter with on-board sample and hold circuitry. The device provides a single pseudo-differential input. Differential Nonlinearity (DNL) is specified at 1 LSB, and Integral Nonlinearity (INL) is offered in 1 LSB (MCP3201-B) and 2 LSB (MCP3201-C) versions. Communication with the device is done using a simple serial interface compatible with the SPI protocol. The device is capable of sample rates of up to 100 ksps at a clock rate of 1.6 MHz. The MCP3201 operates over a broad voltage range (2.7V - 5.5V). Low current design permits operation with typical standby and active currents of only 500 nA and 300 A, respectively. The device is offered in 8-pin MSOP, PDIP, TSSOP and 150 mil SOIC packages. Shift Register CS/SHDN CLK DOUT (c) 2007 Microchip Technology Inc. DS21290D-page 1 MCP3201 1.0 1.1 ELECTRICAL CHARACTERISTICS Maximum Ratings* PIN FUNCTION TABLE Name Function VDD VSS IN+ INCLK DOUT CS/SHDN VREF +2.7V to 5.5V Power Supply Ground Positive Analog Input Negative Analog Input Serial Clock Serial Data Out Chip Select/Shutdown Input Reference Voltage Input VDD.........................................................................7.0V All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V Storage temperature ..........................-65C to +150C Ambient temp. with power applied .....-65C to +125C ESD protection on all pins (HBM)....................... > 4 kV *Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40C to +85C, fSAMPLE = 100 ksps, and fCLK = 16*fSAMPLE unless otherwise noted. Parameter Conversion Rate: Conversion Time Analog Input Sample Time Throughput Rate DC Accuracy: Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Dynamic Performance: Total Harmonic Distortion Signal to (SINAD) Noise and Distortion THD SINAD SFDR -- -- -- 0.25 -- -- -82 72 86 -- 100 .001 -- -- -- VDD 150 3 dB dB dB V A A VIN = 0.1V to 4.9V@1 kHz VIN = 0.1V to 4.9V@1 kHz VIN = 0.1V to 4.9V@1 kHz Note 2 CS = VDD = 5V INL DNL -- -- -- -- -- 12 0.75 1 0.5 1.25 1.25 1 2 1 3 5 bits LSB LSB LSB LSB LSB MCP3201-B MCP3201-C No missing codes over temperature tCONV tSAMPLE fSAMPLE -- -- -- 1.5 -- 100 50 12 clock cycles clock cycles ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V Sym Min Typ Max Units Conditions Spurious Free Dynamic Range Reference Input: Voltage Range Current Drain Analog Inputs: Input Voltage Range (IN+) Input Voltage Range (IN-) Leakage Current Switch Resistance Note 1: 2: 3: IN+ IN- INVSS-100 -- -- VREF+INVSS+100 V mV A W See Figure 4-1 0.001 1K 1 -- RSS -- This parameter is established by characterization and not 100% tested. See graph that relates linearity performance to VREF level. Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 for more information. DS21290D-page 2 (c) 2007 Microchip Technology Inc. MCP3201 ELECTRICAL CHARACTERISTICS (CONTINUED) All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40C to +85C, fSAMPLE = 100 ksps, and fCLK = 16*fSAMPLE unless otherwise noted. Parameter Sample Capacitor Digital Input/Output: Data Coding Format High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current Pin Capacitance (all inputs/outputs) Timing Parameters: Clock Frequency Clock High Time Clock Low Time CS Fall To First Rising CLK Edge CLK Fall To Output Data Valid CLK Fall To Output Enable CS Rise To Output Disable CS Disable Time DOUT Rise Time DOUT Fall Time Power Requirements: Operating Voltage Operating Current Standby Current Temperature Ranges: Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistance: Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-MSOP Thermal Resistance, 8L-TSSOP Note 1: 2: 3: qJA qJA qJA qJA -- -- -- -- 85 163 206 124 -- -- -- -- C/W C/W C/W C/W TA TA TA -40 -40 -65 -- -- -- +85 +85 +150 C C C VDD IDD IDDS 2.7 -- -- -- -- 300 210 0.5 5.5 400 -- 2 V A A A VDD = 5.0V, DOUT unloaded VDD = 2.7V, DOUT unloaded CS = VDD = 5.0V fCLK tHI tLO tSUCS tDO tEN tDIS tCSH tR tF -- -- 312 312 100 -- -- -- 625 -- -- -- -- -- -- -- -- -- -- -- -- -- 1.6 0.8 -- -- -- 200 200 100 -- 100 100 MHz MHz ns ns ns ns ns ns ns ns ns See Test Circuits, Figure 1-2 (Note 1) See Test Circuits, Figure 1-2 (Note 1) See Test Circuits, Figure 1-2 See Test Circuits, Figure 1-2 See Test Circuits, Figure 1-2 (Note 1) VDD = 5V (Note 3) VDD = 2.7V (Note 3) VIH VIL VOH VOL ILI ILO CIN, COUT 0.7 VDD -- 4.1 -- -10 -10 -- Straight Binary -- -- -- -- -- -- -- -- 0.3 VDD -- 0.4 10 10 10 V V V V A A pF IOH = -1 mA, VDD = 4.5V IOL = 1 mA, VDD = 4.5V VIN = VSS or VDD VOUT = VSS or VDD VDD = 5.0V (Note 1) TAMB = 25C, f = 1 MHz Sym CSAMPLE Min -- Typ 20 Max -- Units pF Conditions See Figure 4-1 This parameter is established by characterization and not 100% tested. See graph that relates linearity performance to VREF level. Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 for more information. (c) 2007 Microchip Technology Inc. DS21290D-page 3 MCP3201 tCSH CS tSUCS tHI CLK tEN DOUT FIGURE 1-1: HI-Z tDO tR MSB OUT tDIS tF LSB HI-Z tLO NULL BIT Serial Timing. Load circuit for tDIS and tEN Test Point VDD 3 k Test Point DOUT CL = 30 pF 30 pF VSS 3 k tDIS Waveform 2 tEN Waveform tDIS Waveform 1 Load circuit for tR, tF, tDO 1.4V DOUT VDD/2 Voltage Waveforms for tR, tF VOH VOL tR tF CLK DOUT Voltage Waveforms for tEN DOUT CS 1 2 3 4 B9 tEN Voltage Waveforms for tDO CS CLK tDO DOUT Voltage Waveforms for tDIS VIH 90% tDIS DOUT Waveform 2 10% DOUT Waveform 1* * Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. FIGURE 1-2: Test Circuits. DS21290D-page 4 (c) 2007 Microchip Technology Inc. MCP3201 2.0 Note: TYPICAL PERFORMANCE CHARACTERISTICS The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25C 1.0 0.8 0.6 0.4 Positive INL 2.0 1.5 1.0 VDD = V REF = 2.7V Positive INL INL (LSB) INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25 50 75 100 125 150 Negative INL 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 20 40 60 80 100 Negative INL Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-1: Rate. Integral Nonlinearity (INL) vs. Sample FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). 2.0 1.5 1.0 Positive INL 2.0 1.5 1.0 Positive INL V DD = 2.7V FSAMPLE = 50 ksps INL (LSB) 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 1 INL (LSB) 0.5 0.0 -0.5 -1.0 -1.5 -2.0 Negative INL Negative INL 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VREF (V) VREF (V) FIGURE 2-2: Integral Nonlinearity (INL) vs. VREF. FIGURE 2-5: (VDD = 2.7V). Integral Nonlinearity (INL) vs. VREF 1.0 0.8 0.6 0.4 1.0 0.8 0.6 0.4 VDD = VREF = 2.7V FSAMPLE = 50 ksps INL (LSB) INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code Digital Code FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V). (c) 2007 Microchip Technology Inc. DS21290D-page 5 MCP3201 Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25C 1.0 0.8 0.6 0.4 Positive INL 1.0 0.8 0.6 0.4 V DD = VREF = 2.7V FSAMPLE = 50 ksps Positive INL INL (LSB) INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100 Negative INL 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100 Negative INL Temperature (C) Temperature (C) FIGURE 2-7: Temperature. Integral Nonlinearity (INL) vs. FIGURE 2-10: Integral Nonlinearity Temperature (VDD = 2.7V). (INL) vs. 1.0 0.8 0.6 0.4 2.0 1.5 1.0 VDD = VREF = 2.7V DNL (LSB) DNL (LSB) Positive DNL 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25 50 75 100 125 150 Negative DNL 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 20 Positive DNL Negative DNL 40 60 80 100 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-8: Differential Sample Rate. Nonlinearity (DNL) vs. FIGURE 2-11: Differential Sample Rate (VDD = 2.7V). Nonlinearity (DNL) vs. 3.0 2.0 3.0 VDD = 2.7V 2.0 FSAMPLE = 50 ksps Positive DNL DNL (LSB) 1.0 Positive DNL 0.0 Negative DNL -1.0 -2.0 0 1 2 3 4 5 DNL (LSB) 1.0 0.0 -1.0 -2.0 -3.0 0.0 0.5 Negative DNL 1.0 1.5 2.0 2.5 3.0 VREF (V) VREF(V) FIGURE 2-9: VREF. Differential Nonlinearity (DNL) vs. FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF (VDD = 2.7V). DS21290D-page 6 (c) 2007 Microchip Technology Inc. MCP3201 Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25C 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 1.0 0.8 0.6 0.4 V DD = V REF = 2.7V FSAMPLE = 50 ksps DNL (LSB) DNL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code Digital Code FIGURE 2-13: Differential Nonlinearity Code (Representative Part). (DNL) vs. FIGURE 2-16: Differential Nonlinearity Code (Representative Part, VDD = 2.7V). (DNL) vs. 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100 Negative DNL 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 V DD = VREF = 2.7V FSAMPLE = 50 ksps Positive DNL DNL (LSB) DNL (LSB) Positive DNL Negative DNL -50 -25 0 25 50 75 100 Temperature (C) Temperature (C) FIGURE 2-14: Differential Temperature. Nonlinearity (DNL) vs. FIGURE 2-17: Differential Temperature (VDD = 2.7V). Nonlinearity (DNL) vs. 5 4 3 2 1 0 VDD = 5V -1 -2 0 1 2 3 4 5 FSAMPLE = 100 ksps VDD = 2.7V FSAMPLE = 50 ksps 20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 VDD = 2.7V FSAMPLE = 50ksps VDD = 5V FSAMPLE = 100 ksps VREF(V) Offset Error (LSB) Gain Error (LSB) VREF (V) FIGURE 2-15: Gain Error vs. VREF. FIGURE 2-18: Offset Error vs. VREF. (c) 2007 Microchip Technology Inc. DS21290D-page 7 MCP3201 Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25C 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100 VDD = VREF = 5V FSAMPLE = 100 ksps 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 VDD = V REF = 2.7V FSAMPLE = 50 ksps VDD = V REF = 5V FSAMPLE = 100 ksps Temperature (C) Offset Error (LSB) Gain Error (LSB) VDD = VREF = 2.7V FSAMPLE = 50 ksps Temperature (C) FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Offset Error vs. Temperature. 100 90 80 70 VDD = VREF = 5V FSAMPLE = 100 ksps 100 90 80 70 60 50 40 30 20 10 0 VDD = VREF = 2.7V FSAMPLE = 50 ksps VDD = VREF = 5V FSAMPLE = 100 ksps 60 50 40 30 20 10 0 1 10 100 VDD = VREF = 2.7V FSAMPLE = 50 ksps SINAD (dB) SNR (dB) 1 10 100 Input Frequency (kHz) Input Frequency (kHz) FIGURE 2-20: Signal to Noise Ratio (SNR) vs. Input Frequency. FIGURE 2-23: Signal to Noise and Distortion (SINAD) vs. Input Frequency. 0 -10 -20 -30 80 70 60 VDD = VREF = 5V FSAMPLE = 100 ksps SINAD (dB) THD (dB) -40 -50 -60 -70 -80 -90 -100 1 VDD = VREF = 2.7V FSAMPLE = 50 ksps 50 40 30 20 10 0 -40 -35 -30 -25 -20 -15 VDD = VREF = 2.7V FSAMPLE = 50 ksps VDD = V REF = 5V, FSAMPLE = 100 ksps 10 100 -10 -5 0 Input Frequency (kHz) Input Signal Level (dB) FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency. FIGURE 2-24: Signal to Noise and Distortion (SINAD) vs. Input Signal Level. DS21290D-page 8 (c) 2007 Microchip Technology Inc. MCP3201 Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25C 12.00 11.75 11.50 11.25 11.00 10.75 10.50 10.25 10.00 9.75 9.50 9.25 9.00 0.0 0.5 1.0 12.0 11.5 11.0 V DD = 5V FSAMPLE = 100 ksps ENOB (rms) ENOB (rms) VDD = VREF = 5V VDD = VREF = 2.7V FSAMPLE = 50 ksps FSAMPLE =100 ksps 10.5 10.0 9.5 9.0 8.5 8.0 VDD = 2.7V FSAMPLE = 50 ksps 1 10 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VREF (V) Input Frequency (kHz) FIGURE 2-25: Effective Number of Bits (ENOB) vs. VREF. FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency. 100 90 80 70 60 50 40 30 20 10 0 1 10 100 V DD = VREF = 2.7V FSAMPLE = 50 ksps 0 Power Supply Rejection (dB) V DD = VREF = 5V, FSAMPLE = 100 ksps -10 -20 -30 -40 -50 -60 -70 -80 1 10 100 1000 10000 SFDR (dB) Input Frequency (kHz) Ripple Frequency (kHz) FIGURE 2-26: Spurious Free (SFDR) vs. Input Frequency. Dynamic Range FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10000 20000 V DD = VREF = 5V FSAMPLE = 100 ksps 30000 40000 50000 Amplitude (dB) FINPUT = 9.985kHz 4096 points 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5000 10000 VDD = VREF = 2.7V FSAMPLE = 50 ksps FINPUT = 998.76 Hz 4096 points Amplitude (dB) 15000 20000 25000 Frequency (Hz) Frequency (Hz) FIGURE 2-27: Frequency Spectrum of 10 kHz input (Representative Part). FIGURE 2-30: Frequency Spectrum of 1 kHz input (Representative Part, VDD = 2.7V). (c) 2007 Microchip Technology Inc. DS21290D-page 9 MCP3201 Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25C 500 450 400 350 VREF = V DD All points at FCLK = 1.6 MHz, except at VREF = V DD = 2.5V, FCLK = 800 kHz 100 90 80 70 VREF = VDD All points at FCLK = 1.6 MHz, except at VREF = VDD = 2.5V, FCLK = 800 kHz 300 250 200 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 IREF (A) IDD (A) 60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 2-31: IDD vs. VDD. FIGURE 2-34: IREF vs. VDD. 400 350 300 VDD = V REF = 5V 100 90 80 70 VDD = VREF = 5V IDD (A) 250 200 150 100 50 0 10 100 1000 10000 VDD = V REF = 2.7V IREF (A) 60 50 40 30 20 10 0 10 100 1000 10000 V DD = VREF = 2.7V Clock Frequency (kHz) Clock Frequency (kHz) FIGURE 2-32: IDD vs. Clock Frequency. FIGURE 2-35: IREF vs. Clock Frequency. 400 350 300 VDD = VREF = 5V FCLK = 1.6 MHz 100 90 80 70 VDD = VREF = 5V FCLK = 1.6 MHz IREF (A) IDD (A) 250 200 150 100 50 0 -50 -25 0 25 50 75 100 VDD = VREF = 2.7V FCLK = 800 kHz 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 VDD = VREF = 2.7V FCLK = 800 kHz Temperature (C) Temperature (C) FIGURE 2-33: IDD vs. Temperature. FIGURE 2-36: IREF vs. Temperature. DS21290D-page 10 (c) 2007 Microchip Technology Inc. MCP3201 Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25C 80 2.0 Analog Input Leakage (nA) 70 60 VREF = CS = VDD 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 V DD = V REF = 5V FCLK = 1.6 MHz IDDS (pA) 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 0 25 50 75 100 VDD (V) Temperature (C) FIGURE 2-37: IDDS vs. VDD. FIGURE 2-39: Analog Input Leakage Current vs. Temperature. 100.00 VDD = V REF = CS = 5V 10.00 IDDS (nA) 1.00 0.10 0.01 -50 -25 0 25 50 75 100 Temperature (C) FIGURE 2-38: IDDS vs. Temperature. (c) 2007 Microchip Technology Inc. DS21290D-page 11 MCP3201 3.0 3.1 PIN DESCRIPTIONS IN+ Positive analog input. This input can vary from IN- to VREF + IN-. In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor (CSAMPLE). Consequently, a larger source impedance increases the offset, gain, and integral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational amplifier such as the MCP601, which has a closed loop output impedance of tens of ohms. The adverse affects of higher source impedances are shown in Figure 4-2. If the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VREF + (IN-)] - 1 LSB}, then the output code will be FFFh. If the voltage level at IN- is more than 1 LSB below VSS, then the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above Vss, then the FFFh code will not be seen unless the IN+ input level goes above VREF level. 3.2 IN- Negative analog input. This input can vary 100 mV from VSS. 3.3 Chip Select/Shutdown (CS/SHDN) The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conversion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions. 3.4 Serial Clock (CLK) The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 for constraints on clock speed. 4.2 Reference Input 3.5 Serial Data Output (DOUT) The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. The reference input (VREF) determines the analog input voltage range and the LSB size, as shown below. V REF LSB Size = -----------4096 As the reference input is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D Converter is a function of the analog input signal and the reference input as shown below. 4096*VIN Digital Output Code = ----------------------V REF where: VIN = analog input voltage = V(IN+) - V(IN-) VREF = reference voltage When using an external voltage reference device, the system designer should always refer to the manufacturer's recommendations for circuit layout. Any instability in the operation of the reference device will have a direct effect on the operation of the A/D Converter. 4.0 DEVICE OPERATION The MCP3201 A/D Converter employs a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the first rising edge of the serial clock after CS has been pulled low. Following this sample time, the input switch of the converter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 12-bit digital output code. Conversion rates of 100 ksps are possible on the MCP3201. See Section 6.2 for information on minimum clock rates. Communication with the device is done using a 3-wire SPI-compatible interface. 4.1 Analog Inputs The MCP3201 provides a single pseudo-differential input. The IN+ input can range from IN- to VREF (VREF +IN-). The IN- input is limited to 100 mV from the VSS rail. The IN- input can be used to cancel small signal common-mode noise which is present on both the IN+ and IN- inputs. For the A/D Converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. DS21290D-page 12 (c) 2007 Microchip Technology Inc. MCP3201 VDD VT = 0.6V Sampling Switch SS RS = 1 k CSAMPLE = DAC capacitance = 20 pF VSS LEGEND VA Rss CHX CPIN VT ILEAKAGE SS Rs CSAMPLE RSS CHx VA CPIN 7 pF VT = 0.6V ILEAKAGE 1 nA = = = = = = = = = Signal Source Source Impedance Input Channel Pad Input Pin Capacitance Threshold Voltage Leakage Current At The Pin Due To Various Junctions Sampling Switch Sampling Switch Resistor Sample/hold Capacitance FIGURE 4-1: Analog Input Model. 1.8 Clock Frequency (MHz) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 100 1000 VDD = VREF = 5V VDD = VREF = 2.7V 10000 Input Resistance (Ohms) FIGURE 4-2: Maximum Clock Frequency vs. Input Resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions. (c) 2007 Microchip Technology Inc. DS21290D-page 13 MCP3201 5.0 SERIAL COMMUNICATIONS Communication with the device is done using a standard SPI-compatible serial interface. Initiating communication with the MCP3201 begins with the CS going low. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The device will begin to sample the analog input on the first rising edge after CS goes low. The sample period will end in the falling edge of the second clock, at which time the device will output a low null bit. The next 12 clocks will output the result of the convertCYC TCSH sion with MSB first, as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 12 data bits have been transmitted and the device continues to receive clocks while the CS is held low, the device will output the conversion result LSB first, as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. CS TSUCS POWER DOWN CLK TSAMPLE tCONV NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* tDATA** HI-Z NULL BIT B11 B10 B9 B8 DOUT HI-Z * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followed by zeros indefinitely. See Figure below. ** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros. FIGURE 5-1: Communication with MCP3201 using MSB first Format. tCYC tCSH CS tSUCS POWER DOWN CLK tSAMPLE tCONV NULL BIT tDATA** B2 B3 B4 B5 B6 B7 B8 B9 B10 B11* DOUT HI-Z B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 HI-Z * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. ** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros. FIGURE 5-2: Communication with MCP3201 using LSB first Format. DS21290D-page 14 (c) 2007 Microchip Technology Inc. MCP3201 6.0 6.1 APPLICATIONS INFORMATION Using the MCP3201 with Microcontroller SPI Ports With most microcontroller SPI ports, it is required to clock out eight bits at a time. If this is the case, it will be necessary to provide more clocks than are required for the MCP3201. As an example, Figure 6-1 and Figure 6-2 show how the MCP3201 can be interfaced to a microcontroller with a standard SPI port. Since the MCP3201 always clocks data out on the falling edge of clock, the MCU SPI port must be configured to match this operation. SPI Mode 0,0 (clock idles low) and SPI Mode 1,1 (clock idles high) are both compatible with the MCP3201. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the CLK from the microcontroller idles in the `low' state. As shown in the diagram, the MSB is clocked out of the A/D Converter on the falling edge of the third clock pulse. After the first eight clocks have been sent to the device, the micro- controller's receive buffer will contain two unknown bits (the output is at high impedance for the first two clocks), the null bit and the highest order five bits of the conversion. After the second eight clocks have been sent to the device, the MCU receive register will contain the lowest order seven bits and the B1 bit repeated as the A/D Converter has begun to shift out LSB first data with the extra clock. Typical procedure would then call for the lower order byte of data to be shifted right by one bit to remove the extra B1 bit. The B7 bit is then transferred from the high order byte to the lower order byte, and then the higher order byte is shifted one bit to the right as well. Easier manipulation of the converted data can be obtained by using this method. Figure 6-2 shows the same thing in SPI Mode 1,1 which requires that the clock idles in the high state. As with mode 0,0, the A/D Converter outputs data on the falling edge of the clock and the MCU latches data from the A/D Converter in on the rising edge of the clock. CS MCU latches data from A/D Converter on rising edges of SCLK CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data is clocked out of A/D Converter on falling edges DOUT HI-Z NULL B11 B10 BIT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 HI-Z LSB first data begins to come out ? ? 0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low). CS MCU latches data from A/D Converter on rising edges of SCLK CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data is clocked out of A/D Converter on falling edges DOUT HI-Z NULL B11 B10 BIT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 HI-Z LSB first data begins to come out ? ? 0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high). (c) 2007 Microchip Technology Inc. DS21290D-page 15 MCP3201 6.2 Maintaining Minimum Clock Speed 6.4 Layout Considerations When the MCP3201 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. At 85C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.2 ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 12 data bits have been clocked out must not exceed 1.2 ms (effective clock frequency of 10 kHz). Failure to meet this criteria may induce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D Converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met. When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 1 F is recommended. Digital and analog traces should be separated as much as possible on the board and no traces should run underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a "star" configuration can also reduce noise by eliminating current return paths and associated errors. See Figure 6-4. For more information on layout tips when using A/D Converter, refer to AN688 "Layout Tips for 12-Bit A/D Converter Applications". VDD Connection 6.3 Buffering/Filtering the Analog Inputs If the signal source for the A/D Converter is not a low impedance source, it will have to be buffered or inaccurate conversion results may occur. See Figure 4-2. It is also recommended that a filter be used to eliminate any signals that may be aliased back into the conversion results. This is illustrated in Figure 6-3 where an op amp is used to drive the analog input of the MCP3201. This amplifier provides a low impedance source for the converter input and a low pass filter, which eliminates unwanted high frequency noise. Low pass (anti-aliasing) filters can be designed using Microchip's interactive FilterLabTM software. FilterLab will calculate capacitor and resistor values, as well as determine the number of poles that are required for the application. For more information on filtering signals, see the application note AN699 "Anti-Aliasing Analog Filters for Data Acquisition Systems." VDD 4.096V Reference 0.1 F 10 F MCP1541 CL VREF IN+ MCP3201 R1 C1 R2 C2 R3 R4 MCP601 + IN1 F 10 F Device 1 Device 4 Device 3 Device 2 FIGURE 6-4: VDD traces arranged in a `Star' configuration in order to reduce errors caused by current return paths. VIN FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order anti-aliasing filter for the signal being converted by the MCP3201. (c) 2007 Microchip Technology Inc. DS21290D-page 16 MCP3201 7.0 7.1 PACKAGING INFORMATION Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP3201 I/PNNN e3 0725 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Example: MCP3201 ISN e3 0725 NNN 8-Lead MSOP XXXXXX YWWNNN Example: 3201I e3 725NNN 8-Lead TSSOP XXXX YYWW NNN Example: 3201 e3 0725 NNN Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2007 Microchip Technology Inc. DS21290D-page 17 MCP3201 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 D 3 E A2 A A1 e b1 b L c eB Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing N e A A2 A1 E E1 D L c b1 b eB - .115 .015 .290 .240 .348 .115 .008 .040 .014 - MIN INCHES NOM 8 .100 BSC - .130 - .310 .250 .365 .130 .010 .060 .018 - .210 .195 - .325 .280 .400 .150 .015 .070 .022 MAX .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-018B DS21290D-page 18 (c) 2007 Microchip Technology Inc. MCP3201 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e N E E1 NOTE 1 1 2 3 b h c h A A2 A1 L L1 Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer (optional) Foot Length Footprint Foot Angle Lead Thickness Lead Width Mold Draft Angle Top N e A A2 A1 E E1 D h L L1 c b 0 0.17 0.31 5 0.25 0.40 - 1.25 0.10 MIN MILLMETERS NOM 8 1.27 BSC - - - 6.00 BSC 3.90 BSC 4.90 BSC - - 1.04 REF - - - - 8 0.25 0.51 15 0.50 1.27 1.75 - 0.25 MAX Mold Draft Angle Bottom 5 - 15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-057B (c) 2007 Microchip Technology Inc. DS21290D-page 19 MCP3201 8-Lead Plastic Micro Small Outline Package (MS) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 b A A2 c e A1 Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint Foot Angle Lead Thickness N e A A2 A1 E E1 D L L1 c L1 MILLIMETERS MIN NOM 8 0.65 BSC - 0.75 0.00 - 0.85 - 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0 0.08 0.60 0.95 REF - - 8 0.23 0.80 1.10 0.95 0.15 MAX L Lead Width b 0.22 - 0.40 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-111B DS21290D-page 20 (c) 2007 Microchip Technology Inc. MCP3201 8-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 b 2 e c A A2 A1 L1 L Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Footprint Foot Angle Lead Thickness N e A A2 A1 E E1 D L L1 c 0 0.09 4.30 2.90 0.45 - 0.80 0.05 MIN MILLIMETERS NOM 8 0.65 BSC - 1.00 - 6.40 BSC 4.40 3.00 0.60 1.00 REF - - 8 0.20 4.50 3.10 0.75 1.20 1.05 0.15 MAX Lead Width b 0.19 - 0.30 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-086B (c) 2007 Microchip Technology Inc. DS21290D-page 21 MCP3201 NOTES: DS21290D-page 22 (c) 2007 Microchip Technology Inc. MCP3201 APPENDIX A: REVISION HISTORY Revision D (January 2007) This revision includes updates to the packaging diagrams. (c) 2007 Microchip Technology Inc. DS21290D-page 23 MCP3201 NOTES: DS21290D-page 24 (c) 2007 Microchip Technology Inc. MCP3201 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples: a) MCP3201-I/P: Industrial Temperature, PDIP package. b) Device: MCP3201: 12-Bit A/D Converter w/SPI Interface MCP3201T: 12-Bit A/D Converter w/SPI Interface (Tape and Reel) (SOIC and TSSOP only) MCP3201-I/SN: Industrial Temperature, SOIC package. MCP3201-I/ST: Industrial Temperature, TSSOP package. MCP3201-I/MS: Industrial Temperature, MSOP package. c) d) Temperature Range: I = -40C to +85C Package: MS P SN ST = = = = Plastic Micro Small Outline (MSOP), 8-lead Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 8-lead Plastic TSSOP (4.4 mm), 8-lead (c) 2007 Microchip Technology Inc. DS21290D-page25 MCP3201 NOTES: DS21290D-page 26 (c) 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2007 Microchip Technology Inc. DS21290D-page 27 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 12/08/06 DS21290D-page 28 (c) 2007 Microchip Technology Inc. |
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